This invention relates to semiconductor devices comprising a semiconductor device body encapsulated in an envelope of synthetic resin material, particularly but not exclusively power devices that include an integrated circuit (herein termed xe2x80x9cICxe2x80x9d) in the device body. The invention also relates to their advantageous manufacture. The device body is often termed xe2x80x9cchipxe2x80x9d.
In power ICs with fine dimensions and in power devices with integrated control circuitry (so-called xe2x80x9cSmart Powerxe2x80x9d devices), the top surface of the chip may be highly corrugated (at least locally) from a topography of fine metal lines that run over the chip. These metal lines are part of a pattern of conductive connections present on (and at windows in) an insulating layer at that surface of the chip. Typically the metal lines are narrow (e.g. one to five micrometers wide), but they may be quite thick (e.g. one to five micrometers) so as to provide low electrical resistance and freedom from electro-migration effects. Particular examples of such power devices are disclosed in United States patent specification U.S. Pat. No. 4,929,884 (our ref. PHB33363) and more recent, published PCT patent application WO-A-00/62422 (our ref. PHB34338), the whole contents of which are hereby incorporated herein as reference material.
Usually the chip is covered by an insulating over-layer (sometimes called a xe2x80x9cglass-overxe2x80x9d) of a dielectric material such as silicon nitride or oxide or a polyimide. These layers are typically brittle. The insulating over-layer extends over the pattern of conductive connections and protects the chip from the ingress of contaminants such as water and sodium. Metal bond pads are connected to appropriate ones of the conductive connections, at windows in the over-layer. Terminal conductors (such as the terminal leads of a lead-frame of the device) are connected to the metal bond pads within the envelope, for example by wire-bonding. When assembled into a hard plastic package (an envelope of synthetic resin material), the plastic material normally adheres well to the insulating over-layer, because such synthetic resin compounds are designed to have high adhesion and to provide a good seal.
The plastic material, bulk semiconductor material and lead-frame material expand and contract to differing degrees during thermal cycling in operation of the device, or when the device is cycled between temperatures on a reliability test or simulated application test. The differential expansion and contraction give rise to high stress in the package. This stress is particularly high at the plastic to chip interface, where it can lead to cracking of the insulating over-layer and to distortion and/or shifting of the metal lines.
The top metal of the conductive connections and of the bond pads is often aluminium with a small amount of Si or Cu added. It is quite soft and can be detached and/or distorted (smeared) by the stress. The insulating over-layer is generally a rigid layer that cannot be deformed; it reacts to the stress by cracking.
The cracking of the insulating over-layer can result in contamination of the chip by the ingress of, for example, water and sodium that degrade the electrical stability of the chip. The stress effects on the conductive connections can lead to an effect sometimes called xe2x80x9cPattern Shiftxe2x80x9d, in which electrical failure can even occur by short-circuiting or open-circuiting of the metal connections. The corrugation of the chip surface exacerbates the problem, as it allows a good keying of the plastic material to the insulating over-layer. The problem is often most severe towards the corners of the chip.
In order to protect the metal connections of an integrated circuit device against such damage due to stress, published Japanese patent application Kokai JP-A-04-28254 proposes covering the insulating over-layer with a thick layer of ductile metal (aluminium). The whole contents of JP-A-04-28254 are hereby incorporated herein as reference material.
This thick aluminium layer of JP-A-04-28254 provides an interface with the synthetic resin material that reduces stress between the insulating material and the synthetic resin material during thermal cycling of the device. The layer is provided everywhere on the insulating over-layer, regardless of the nature of the underlying device elements, and it is absent from the bond pad areas of the device. The present inventor finds that this layer provision can be incompatible with some device structures and can be significantly improved.
It is an aim of the present invention to reduce stress between the insulating over-layer and the synthetic resin material of the package/envelope during thermal cycling of the device, and to reduce the effect of the stress on the underlying conductive connections. It is a further aim of the invention to provide an appropriate novel interface between these insulating and synthetic resin materials, having regard to the electrical properties of the underlying conductive pattern and its insulating over-layer.
According to the present invention, there is provided a semiconductor device comprising a semiconductor device body encapsulated in an envelope of synthetic resin material, wherein the device body is provided at its upper surface with a ductile layer pattern over most of the surface area of the insulating over-layer of the body. This ductile covering provides a yielding interface that reduces stress between the insulating material and the plastic material during thermal cycling of the device. In accordance with the invention, the ductile layer is provided in a pattern of laterally separate parts that are electrically isolated from each other. This electrical isolation permits the ductile layer pattern to be arranged in an electrically compatible manner with the electrical potentials (that occur in operation of the device) at the underlying areas of the conductive pattern and its insulating over-layer. A number of the electrically-isolated parts of the ductile metal layer pattern may even form metal bond pads of the device, for example at windows in the insulating over-layer. The spacing of the electrically-isolated parts of the pattern is sufficient to avoid a short circuit there-between as a result of the lateral deformation of the ductile metal during thermal cycling.
Such a semiconductor device in accordance with the invention may have the features as set out in claim 1. Particular preferred features are set out in the remaining claims. In a particularly convenient and simple form, a single patterned layer of deposited aluminium (or aluminium alloy) may provide the interface in accordance with the invention.
The ductile metal layer pattern acts like a soft covering to protect the vulnerable features underneath. Although distorted during cyclic stress, it can readily deform and thereby accommodate movement without any failure of the active regions underneath. For this reason, it is generally advantageous for the ductile metal to be thicker than height variations in the underlying surface of the insulating over-layer.
Such a ductile interface can be particularly advantageous over an IC area of a power device, where the insulating over-layer is corrugated by extending over connection tracks of the conductive pattern. Thus, the IC area can be protected from the effects of thermal stress by covering its insulating top area with one or more parts of the ductile layer pattern. Another part of the ductile layer pattern can be associated with another part of the device, for example a power dissipation area of the chip. When the device comprises a capacitor, one or more of the capacitor plates can be a sizeable metal area. In this case, it is advantageous for at least one of the electrically-isolated parts of the ductile metal layer pattern to extend on and/or form an upper plate of the capacitor.
Thus, it is a particularly advantageous feature of the invention that the ductile metal layer pattern comprises electrically-isolated parts that are appropriately spaced from each other on the insulating over-layer. As the underlying conductive areas of the device are generally at different potentials to each other, it is advantageous to connect one or more of the electrically-isolated parts of the layer pattern individually to an appropriate potential (for example, of a respective underlying conductive area) so as to reduce charging effects across the insulating over-layer. These electrically-isolated parts can be readily spaced sufficiently from each other to avoid a short circuit between the electrically-isolated parts as a result of lateral deformation (shearing and smearing) of the ductile metal during thermal cycling of the device.
Standard device processing can be used to form this ductile metal pattern in a high-volume manufacturing context. Thus, the metal layer can be both easily and cheaply applied to a semiconductor wafer before dividing the wafer into individual chips. Standard deposition and etching technologies may be used. The same deposited layer may even be patterned to provide also the bond pads of each chip, and so no additional processing steps may be necessary. These are potentially important manufacturing process aspects of the present invention.